Information need not be passed down through physical means like mail or newspapers. It can be done through SMS (short messaging service), a phone call or even an email. Underlying such great inventions is the use of electronic devices to transmit and receive signals. Due to the demand for faster and larger data flow, complex systems such as Code-Division Multiple Access (CDMA) have been developed. This project is confined to the fundamental concepts used in digital communication. These key concepts include sampling, quantization and frame synchronization.
The circuit designed is meant for one-way dataflow. It supports transmission by one user from any analog input. Hence, it is not necessary to select between multiple analog inputs using the frequency-division multiplexing technique. In transmitting wirelessly, a laser and photodiode are used instead of antennas. This choice is made because it is complex to build a Frequency Shift Keying (FSK) circuit. Without FSK, an antenna would need to be 75km long in order to transmit a wave of 4 kHz. 1. 2 Problem Identification In this project, a laser pointer is used to transmit analog signal wirelessly.
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In order to realize digital transmission, the analog signal must be converted into digital form using a Pulse Code Modulation (PCM) encoder. Before the signal can be decoded at the receiver end, frame synchronization must be achieved. Hence, a training sequence must be sent to synchronize the receiver and transmitter. Next, a Digital Phase Locked Loop (DPLL) is needed to lock on to the transmitted signal and generate clocks at the receiver end. In the final stage, the digital signal is converted back to an analog signal. This signal is then played through a speaker. 1. 3 Constraints Availability of Manpower
Our main constraint lies in the shortage of manpower. Due to the complexity of the DPLL Circuit and Training Sequence Identification Circuit, more members should be allocated to these two subgroups. However, this is not possible as our group consists of only eight members. This constraint will be addressed in the implementation section of this report. Components The design of any combinational logic circuit is confined to the availability of chips (gates). In this project, we are not provided with AND and NOR gates. Hence, knowledge of Boolean algebra will aid us in realizing any logic with the universal NAND gate.
In addition, the design of logic circuits also depends on the space of breadboard. Hence, minimizing the number of chips used takes higher precedence over the simplicity of design. This is to achieve compactness on the breadboard. Time A short time frame of seven weeks is given to build a laser communication system. Apart from building the prototype, our group must submit design and final reports for grading. Hence, it is critical that all group members adhere to the schedule.
Further, since there are no extra lab sessions provided for testing and debugging, subgroups must build the circuits before going for the lab session. . System Design 2. 1 Project Requirements 1. 2. 048 MHz Master Clock, 64 KHz Bit Clock and 8 KHz Frame Synchronization: with rising edges aligned. 2. Clock signals into PCM encoder, training sequence generator and multiplexer. 3. Coder and decoder chips are needed for analog to digital conversion and digital to analog conversion respectively. 4. Model the photodiode as a voltage source. 5. Yield minimal noise in the photodiode circuit. 6. DPLL: Determine the value of K, N, M and constant phase difference between local clock and data sequence. 7. DPLL: Design a divide by N Counter. 8. Frame synchronization must be achieved. 9.
Training Sequence must be generated. 10. A D flip-flop is required to switch training frame to data frame at the correct instance. 11. A logic circuit must be implemented to identify the training sequence at the receiver end. 12. Implement a “Divide by 8” counter to yield 8 KHz Frame Synchronization Receiver from the 64 KHz Bit Clock. 2. 2 Design of System The system consists of two functional components. They are the transmitter and receiver. In the discussion of this system, the transmitter side will be first discussed followed by the receiver end. 2. 3 Design of Transmitter The transmitter consists of several sub-blocks.
These sub-blocks include the clock and counter networks, training sequence generator, switch, encoder and the laser link. 2. 3. 1 Clock and Counter Networks In this system, 2. 048MHz Master Clock (MCLK), 64 KHz Bit Clock (BCLK) and 8 KHz Frame Synchronization Signal (FSYN) are required. BCLK and FSYN are required by the training sequence generator and multiplexer (MUX) switch respectively. The encoder chip requires MCLK, BCLK and FSR. As such, the breadboard layout shown in Figure 1 is adopted. Figure 1: Breadboard Layout (Transmitter) Master Clock (MCLK) The Master Clock (MCLK) is obtained from the signal generators available in the lab.
As a high speed clock is needed by the PCM encoder to function, the value of 2. 048 MHz is chosen. MCLK provides the timing signal to synchronize the other clocks in the system. In this manner, the rising edge of the generated BCLK and FSR will coincide with MCLK. Bit Clock (BCLK) The Bit Clock (BCLK) frequency is 64 KHz. This is generated by inputting MCLK into the Counter (74HC191) followed by a D Flip-flop (74HC74). BCLK is required because the frequency of bits generated by the encoder is 64 KHz. The BCLK allows the bit stream to be synchronized with the clock network. Frame Synchronization Signal (FSYN)