Reversible Logic

1 January 2017

It has been shown that the modi? ed designs outperform the existing ones in terms of number of gates, number of garbage outputs, delay, and quantum cost. In order to show the ef? ciency of the proposed designs, lower bounds of the reversible BCD adders in terms of gates and garbage outputs are proposed as well. & 2008 Elsevier Ltd. All rights reserved. 1. Introduction The advancement in higher-level integration and fabrication process has emerged in better logic circuits and energy loss has also been dramatically reduced over the last decades. This trend of reduction of heat in computation also has its physical limit.

We will write a custom essay sample on
Reversible Logic
or any similar topic specifically for you
Do Not Waste
Your Time

According to Landauer [1,2], in logic computation every bit of information loss generates kTln2 joules of heat energy where k is Boltzmann’s constant of 1. 38 A 10A23 J/K and T is the absolute temperature of the environment. At room temperature, the dissipating heat is around 2. 9 A 10A21 J. Energy loss due to Landauer limit is also important as it is likely that the growth of heat generation causing information loss will be noticeable in future.

Reversible circuits are fundamentally different from traditional irreversible ones. In reversible logic, no information is lost, i. e. he circuit that does not lose information is reversible. Bennett [3] showed that zero energy dissipation would be possible if the network consists of reversible gates only. Thus, reversibility will be an essential property for the future circuit design. Quantum computation is also gaining popularity as some exponentially hard problems can be solved in polynomial time [4]. We know that quantum computation is reversible. Thus, research in reversible logic is helpful for the development of future technologies; it has the potential to methods of quantum circuit construction resulting in more powerful computers.

Quantum technology is not the only one where reversibility is used. A Corresponding author. Tel. : +880 1711 351055; fax: +880 2 8615583. E-mail address: ha? [email protected] com (H. M. Hasan Babu). 0026-2692/$ – see front matter & 2008 Elsevier Ltd. All rights reserved. doi:10. 1016/j. mejo. 2008. 04. 003 Reversible logic has also found its applications in several other disciplines such as nanotechnology [5], DNA technology [6] and optical computing [7]. In computers, numbers are stored in straight binary format. Due to inherent characteristics of ? oating-point numbers and limitations on storing formats, not all ? ating-point numbers can be represented with desired precision.

So, computing in decimal format is gaining popularity as loss due to precision can be avoided in this format. However, hardware support for binary arithmetic allows it to be performed faster than decimal arithmetic. Faster hardware for decimal ? oating-point arithmetic is also imminent as it has its importance in ? nancial and Internet based applications. So, faster circuits for Binary Coded Decimal (BCD) numbers have great impact, as it is likely to be incorporated in more complex circuits like future mathematical processors.

Reversible logic implementations for BCD adder as well as Carry Skip BCD adder are presented in Refs. [9,10]. A reversible BCD adder using 4-bit parallel adder is presented in Ref. [9], whereas in Ref. [10], reversible logic implementations for both BCD adder and Carry Skip BCD adder are presented. In this paper, an improved reversible logic implementation for BCD adder is presented. We have compared proposed design with the existing ones and found that modi? ed design is better than the existing ones in terms of number of gates, garbage output (output that is needed to maintain reversibility), delay, and quantum cost.

Secondly, an improved design technique for Carry Skip BCD adder is also presented. It has been found that this design is also better in comparison with the existing one in terms of the aforementioned metrics. ARTICLE IN PRESS 1694 A. K. Biswas et al. / Microelectronics Journal 39 (2008) 1693–1703 Rest of the paper is organized as follows: Section 2 provides the necessary background on reversible logic along with the examples of popular reversible gates. Important terms needed for reversible logic are also de? ned. Quantum cost calculation for different gates is thoroughly discussed in Section 3.

Section 4 provides the basics for reversible logic synthesis and overview of the existing designs. Section 5 provides ef? cient techniques for implementation of BCD adder as well as Carry Skip BCD adder, which overcome the limitations of the existing methods. Algorithms needed for the designs and comparative studies with the existing designs along with the lower bounds for the proposed designs in terms of number of gates and garbage outputs are also provided in that section.

A limited
time offer!
Get authentic custom
ESSAY SAMPLEwritten strictly according
to your requirements